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AES family of accelerators.

Available in 6 configurations / performance grades.

Library element for  security packet engines.

Product description

The AES-IP-36 is a family of the cryptographic library elements in Inside Secure’s HW IP library. For example, the AES-IP-36 is the cipher core embedded in all PacketEngine-IP-97/98/197 protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2.5Gbps to 12.8Gbps depending on the configuration and area. Gate count is between 23K and 52k gates depending on the configuration. Multiple AES-IP-36 cores can be cascaded.

Inside Secure also offers the AES-IP-39 / EIP-39 that supports more AES modes and can be provided including counter measures against side channel attacks and fault injection attacks.

AES-IP-36 for accelerating the AES symmetric cipher algorithm scheme
Other information

Key benefits:

  • Silicon-proven implementation.
  • Fast and easy to integrate into SoCs.
  • Flexible layered design.
  • Complete range of configurations.
  • World-class technical support.


  • Wide bus interface (128 bit data, 256 bit keys) or 32 bit register interface.
  • Key sizes: 128, 192 and 256 bits.
  • Includes key scheduling hardware.
  • Feedback modes: ECB, CBC, CTR, OFB (128 bit), 
CFB (1-, 8- and 128-bit). 

  • Fully synchronous design.
  • Low Speed, Medium Speed, High Speed versions.
  • Encrypt-only versions (aimed at Counter Mode) for 
each speed version.
  • Fully synchronous design.


  • AES-IP-32 / EIP-32 AES ECB accelerators
  • AES-IP-36 / EIP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 / EIP-37 AES Key Wrap accelerators
  • AES-IP-38 / EIP-38 AES XTS/GCM accelerators
  • AES-IP-39 / EIP-39 AES ECB/CBC/CTR/CCM/GCM accelerators