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3GPP ZUC-48 family of accelerators.

Available in 3 configurations / performance grades.

Targeting Base Station designs.

Product description

The ZUC-IP-48 is a family of the cryptographic library elements in Inside Secure’s HW IP library. For example, the ZUC-IP-48 is the cipher core embedded in some PacketEngine-IP-97/98/197 protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 4Gbps to 20Gbps depending on the configuration, area and frequency. Gate count is 20K..30K gates depending on the configuration. Supported modes: 128-EEA3 and 128-EIA3

Inside Secure also offers accelerators for the other 3GPP algorithms.

ZUC-IP-46 3GPP cipher accelerators scheme
Other information

Key benefits:

  • Silicon-proven implementation.
  • Fast and easy to integrate into SoCs.
  • Flexible layered design.
  • Complete range of configurations.
  • World-class technical support.


  • Wide bus interface (32 bit data, 128 bit keys) or 32 bit register interface.
  • Includes key scheduling hardware.
  • Supported modes: 128-EEA3 and 128-EIA3.
  • Fully synchronous design.
  • Low Speed, High Speed versions.
  • Fully synchronous design.
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