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Secure Hash-based HMAC family of accelerators

Available in several configurations / performance grades

Library element for platform security and packet engines

Product description

The HMAC-IP-59 is a family of the cryptographic library elements in Inside Secure’s HW IP library. For example, the HMAC-IP-59 is the hash core embedded in the IPsec packet engines as well as Vault-IP platform security engines providing support for MD5 and SHA based Hash and HMAC functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2Gbps to 8Gbps, depending on the configuration and area. Gate counts ranges from 23K to 95K gates depending on the configuration. 

HMAC-IP-59 hash based HMAC accelerators scheme
Other information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support


  • Wide bus interface
  • Supporting HMAC and Basic Hash operations for all algorithms: MD5, SHA-1, SHA-2 (224, 256, 384, 512), SHA-3 (224, 256, 384, 512)
  • MAC Key XOR and Message padding
  • Message data scheduling hardware
  • Calculation of “inner digest” and “outer digest” from a MAC Key input
  • Calculation of “inner hash” and “outer hash” from a MAC Key input or “inner digest” and “outer digest” input
  • MAC Key sizes shorter, equal and longer than algorithm block size
  • Hash and HMAC context switching
  • Continued hash / HMAC support
  • Standard, high frequency and high performance versions available
  • Secure hash standard Compliant FIPS-180-2, FIPS-180-3, FIPS-180-4
  • HMAC support for all algorithms, compliant with FIPS-198-1, FIPS-198
  • Fully synchronous design


  • HASH-IP-57 / EIP-57 Hash MD5, SHA-1, SHA-2, SHA-3