Circuit Camouflage Technology

Technologies specifically designed for Anti-Tamper, Intellectual Property protection and Cloning Prevention

With worldwide applications rights and over 50 granted US patents and numerous international patents, Inside Secure has developed the know-how and proprietary trade secret techniques uniquely positioned to implement these designs. We offer training and licensing options, enabling your design team to implement SML circuit camouflage technology on your devices as well as a range of courses in hardening silicon IP to reverse engineering, cloning, and tamper attacks.

The Circuit Camouflage Technology has never been successfully reverse engineered leading to a pirated part. SML is a unique and innovative technology that when incorporated into an ASIC design, makes the silicon itself resisting reverse-engineering attacks. SML utilizes foundry standard cells, standard tools and design methodology, doesn’t rely on coatings or shields, and provides a high return on investment for silicon manufacturers, chip makers wanting Intellectual Property protection and having products in high attack environments.

The SML is available in silicon technologies down to 28nm and Inside Secure is currently working on a project in FINFET 14nm.

Extend the lifetime of your silicon designs and protect your critical intellectual property

Using these designs and techniques, chip makers keep sensitive and strategic aspects of custom designs secret from competitors and counterfeiters, providing hardware protection to secure intellectual properties. Additionally, Inside Secure's Camo SmartFill provides high tamper resistance from unauthorized modifications to the design by filling the entire chip with circuitry allowing attackers no space in which to insert a Trojan circuit without destroying the underlying function of the ASIC.

In summary, Inside Secures's Circuit Camouflage Technology together with Camo SmartFill:

• Keeps designs secret from competitors and counterfeiters 
• Protects against state-of-the-art circuit extraction attacks
• Is applicable to any CMOS process and any digital design
• Significantly extends the security life of your product
• Is low-risk technology that has been in practice for over 20 years
• Easily applies to any standard cell design flow
• Minimal impacts area, performance, and power consumption
• Camouflage of analog IP is also available
• Secures design during device manufacturing

Normal AND2 gate

Camouflage AND2 gate

The camouflage AND2 gate appears identical to the normal AND2 gate. It performs a different logic function. A reverse engineer mistakenly interpreting both gates as normal AND2 gates would extract an incorrect netlist from silicon.