Secure Hash family of accelerators.
Available in several configurations / performance grades.
Library element for platform security and packet engines.
The HASH-IP-57 is a family of the cryptographic library elements in Inside Secure’s HW IP library. For example, the HASH-IP-57 is the hash core embedded in the IPsec packet engines as well as Vault-IP platform security engines providing support for MD5 and SHA Hash based functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges from 2Gbps to 84Gbps depending on the configuration and area. Gate counts ranges from 14K to 49K gates depending on the configuration.
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
- Wide bus interface (1024 bit data, 512 bit digest) or 32 bit register interface
- MD5, SHA-1, SHA-2, SHA-3
- SHA-2/3 in 224/256/384/512 modes
- Message puffing for all algorithms
- Message data scheduling hardware
- Hash context switching and state loading
- Standard, high frequency and high performance versions available
- Fully synchronous design
- HMAC-IP-59 / EIP-59 MD5, SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators