HDCP content protection data path

Up to 20Gbps HDCP 1.4 & 2.2

Targets HDMI, MHL, HDBaseT or DisplayPort devices

Product description

The HDCP-IP-114 (EIP-114) HDCPv1.4 & v2.2 content protection datapath engine is a cryptographic accelerator designed to encrypt HDMI, HDBaseT, MHL or DisplayPort video/audio data streams. In addition, the HDCP-IP-114 can offload part of the CPU intensive authentication operations of HDCP1.

The cipher module of the HDCP-IP-114 is suited for HDCP1 and HDCP2 data lane encryption and can achieve throughputs up to 17Gbps at 540MHz for DisplayPort or 14.4 Gbps at 600MHz for HDMI, supporting SD, HD and UHD video streams (up to 4096x2160p60).

Depending on the chosen configuration, the HDCP-IP-114 targets either HDMI, MHL, HDBaseT or DisplayPort devices. For DisplayPort it includes all functionality to replace and adjust the data lane control symbols related to the encryption (DPES). Three DisplayPort configurations are available, supporting 1, 2 or 4 data lanes.

For HDMI it includes generation and detection of encryption status signaling (OESS and EESS).

The HDCP-IP-114 is part of Inside Secure’s HDCP product offering which consists of data lane encryption modules, full HDCP security modules and HDCP software components. Multiple HDCP-IP-114 instances can be controlled by one instance of the VaultIP-130 security module loaded with HDCP SW.

Other information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
  • Separate HDCP SW stack available

Supported content interfaces:

  • HDMI 1.4 & 2.0
  • DisplayPort 1.2 & 1.3
  • MHL 1.4, 2.2 & 3.2
  • HDBaseT 2.0

HDCP1 crypto algorithm

  • RNG function (hdcpRngFunction) with seeding
  • Authentication HDCP1 cipher operation
  • Data lane encryption for 1, 2 or 4 DisplayPort lanes, achieving 5.4Gbps of link rate per lane
  • HDMI data path encryption for speeds up to 14.4Gbps at 600MHz
  • Generation of HDCP1 enhanced link verification information for HDMI

HDCP2 crypto algorithm

  • AES with a key length of 128 bits
  • Offloading of AES operations required during AKE
  • Data lane encryption for 1, 2 or 4 DisplayPort lanes, achieving 5.4Gbps of link rate per lane
  • HDMI data path encryption for speeds up to 14.4Gbps at 600MHz

Secure access of confidential material

  • Hardware protected access via the Host bus interface using protection bits

Interfaces

  • The EIP-114 has a single 32-bit host APB interface that has its own interface clock signal. It can operate fully asynchronous from the module clock. The host interface directly connects to a EIP-116 HDCP control module, but it can also connect to an external host CPU that runs the HDCP SW stack.

DisplayPort or HDMI data path

  • DisplayPort: 32-bit wide data bus per DisplayPort data lane
  • HDMI: shared 24-bit data lane for HDMI Video and Auxiliary data; backwards compatible with DVI
  • HD-Base-T: combined with HDMI / MHL
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