"Driving trust for adaptable SoC / ASIC security architecture in the new connected world"

Adaptable SoC / ASIC security architecture

Security is the primary challenge

Security challenges and threats continue to make headlines in our connected world. Everything connected - cars, lighting systems, smartwatches, white goods, home security devices, medical equipment, airplanes, industrial automation systems… - are vulnerable to cyber security attacks.

Finding the best balance between security, cost and performance

With frequent headlines on cyber security attacks, semiconductor makers, FPGA providers are serious about security, making smart decisions that lead to an optimal balance between security, cost and performance.

Solutions need to specifically crafted for SoCs or ASICs, for the types of threats that the connected devices will be exposed to. To secure these devices, designers need a comprehensive security IP framework that provides the right level of security with the right functions in these devices.

Experience Inside Secure’s best-in-class technology for your SoCs and ASICs!

MACsec Engines

Silicon IP

A complete solution comprising of a family of MACsec Security IP and a MACsec software toolkit targeting PHY devices, switches, bridges, and routers for Layer 2 LAN and Metro Ethernet communications. The MACsec engines target deployments in data centers, 5G base stations, enterprise networks, home gateways, IP phones and more. Build Ethernet switch fabrics and PHY devices using MACsec engines to reach speeds from 1Gbps, 10Gbps, 100Gbps, 400Gbps and beyond. The IP provides a complete and standard compliant MACsec solution, which ensures auditable compliance while reducing development cost and time to market. 

Unlike simple crypto-only accelerators, intelligent packet engines contain complete protocol knowledge, delivering the benefits of throughput acceleration and CPU offload. The Multi-Protocol Engine IPs offer acceleration of IPsec, MACsec, SSL/TLS/DTLS, sRTP and basic hash-crypto operations at target speeds ranging from 100Mbps to 50Gbps and beyond, in architectures ranging from the traditional look-aside engines to the more sophisticated, powerful inline packet engines.

Inside Secure’s cryptographic algorithm accelerator IP cores are standalone hardware IP cores for accelerating various symmetric, asymmetric ciphers, HASH and HMAC-based integrity algorithms, as well as true random number generators (TRNG). Vault IP cryptographic engines can be used for accelerating applications for storage, LTE, PKI/PKA infrastructure, HDCP.

Cipher Accelerators

Silicon IP

Inside Secure’s cipher accelerator IP cores are standalone hardware IP cores for accelerating various symmetric and asymmetric cryptographic primitive algorithms. These cores are also embedded in packet engines as well as Vault-IP products.

Inside Secure’s Hash and HMAC accelerator IP cores are standalone hardware IP cores for accelerating various HASH and HMAC-based integrity algorithms. These cores are also embedded in packet engines as well as Vault-IP products.